1. Field of the Invention
The present invention relates to the field of integrated circuit design, specifically to analog signal recording and playback utilizing non-volatile memory integrated circuits.
2. Prior Art
For analog signal recording and playback utilizing nonvolatile memory integrated circuits, as described in the patent numbered U.S. Pat. No. 5,220,531 by Trevor Blyth and Richard Simko, EEPROM (electrically erasable programmable read only memory) memory cells are used. These cells are comprised of a floating gate device having a source, a drain, a gate and a floating gate wherein the threshold of the device as measured between the gate and the source of the device is determined (controlled) by the charge on the floating gate. These cells are erased using Fowler-Nordheim tunneling by applying a high voltage, e.g. 21 V on the gate, zero volts on the source, and zero volts on the drain. The high voltage on the gate capacitively couples to the floating gate, which creates a high electric field through the tunnel oxide between the floating gate and the drain. This electric field causes electrons to tunnel to the floating gate, which effectively raises the Vt (threshold voltage) to about 6 V. Next the cell is programmed using the same Fowler-Nordheim tunneling mechanism by applying a high voltage on the drain, e.g. 9 to 19 volts, zero volts on the gate, and 6 V on the source. The high voltage on the drain causes a high electric field through the tunnel oxide between the floating gate and the drain in the reverse direction. This causes electrons to tunnel from the floating gate to the drain, causing the threshold voltage to be lower (depleted), e.g. -1 V to +3 V, depending on the voltage level on the drain and the pulse width.
In U.S. Pat. No. 5,220,531, the program "pulse" is divided into a series of coarse pulses and a series of fine pulses to store an analog signal in the non-volatile memory cell. After each programming pulse, the content of the cell is read using a read cycle and compared with the analog signal to be stored, with the coarse pulses terminating when the desired programmed level is approached, and the fine pulses terminating when the desired programmed level is reached. The coarse write/read/compare series followed by the fine write/read/compare series provides superior analog signal resolution in the stored signal.
In the above patent, the dynamic range of the cell is about 3 V, with an analog resolution of about 12 millivolts, giving an effective resolution equivalent to a digital storage of 8 bits (each cell has a resolution of 12/3000, or about 1 part in 250). Each coarse pulse or fine pulse is divided into a ramp up time portion and a flat time portion equally of the high voltage, and a sample and compare enable time portion. The compare time portion is used to read back the voltage stored in the memory cell after each incremental coarse or fine programming pulse to see if it reaches a desired value. The sample time portion is used to sample the next sample of input signal and hold it. The sample and compare time portion is the quiet time, i.e. the high voltage source such as the charge pump is disabled for noise reasons. The step voltage between successive coarse levels is approximately 220 millivolts and the step voltage between successive fine levels is approximately 22 millivolts, which is equivalent to a resolution of 12 mV in the stored voltage in the memory cell. The large step voltage for the coarse levels is required to cover the full range of the cell programming threshold window plus an additional voltage margin, which ranges from approximately 9 to 19 volts on the drain of the memory cell, corresponding to about 0-3 v of the memory cell threshold voltage, approximately the analog dynamic range of the memory cell. The number of coarse pulses available is chosen to be 45, which translates into 45.times.220 mV=10 volts full range. The large coarse step is used to achieve the short writing time. The fine ramp full range is chosen to be about 2 V. 90 fine pulses are available, giving a writing resolution of about 22 mV. Thus the number of column sample and hold/high voltage drivers is defined by the sampling rate together with the cell programming time. For example, for sampling rate of 8 Khz (typical audio signal), and a cell programming time of 12.5 ms with the above coarse and fine pulses, the number of column sample and hold/high voltage drivers are 12.5 ms/125 .mu.s=100. This also means the cell writing is happening for 100 columns at the same time.
In the read mode, the storage cell is configured as a source follower with a constant load current from the drain to ground. The gate and the source of the memory cell are connected together, the drain of the memory cell is connected to a constant bias current, the gate of the select transistor is connected to an intermediate voltage, e.g. 10 V, to eliminate the gate voltage drop effect and the resistive effect from the small size of the select gate. A regulated power supply, e.g. 4 V, is connected to the gate/source of the memory cell to avoid the variation of the gate/source voltage on the cell readout voltage. The voltage at the drain is the memory cell readout voltage. Thus the cell is connected as a source follower with the drain and source interchanged. This results in a linear relationship between the threshold of the cell and the cell readout voltage. The storage cell is thus operated in the saturation region since the gate and source are effectively tied together.
In this read configuration, severe disadvantages are encountered when used in a configuration wherein there are series parasitic resistive effects on the source node or the drain node, or there are large variations in the transistor conductances such as are caused by mobility or threshold voltage variations over temperature, process variations or power supply variations. The series parasitic resistive effects, for example, come from the source diffusion resistance of the memory cells, or from other series transistors as in a string memory cell structure such as in a NAND flash memory cell. The source line is typically strapped, e.g., for every 32 cells, by metal or select transistors to reduce resistance from the source line diffusion. Even so, the resistance from the source line diffusion is still very significant, especially for multilevel storage wherein each discrete storage level is to be discernible on readout from each other discrete level. Furthermore, the more effective the strap in reducing these effects, the more strap area is used, resulting in a larger die size.
The NAND memory cell consists of a string of, for example, 8 memory cells in series, and 2 select transistors to select the memory string, one select transistor contact being shared with another memory cell string. Since in effect there is only one-half a bitline contact and one-half a common source line for the 8 memory cells, the per-cell area of the NAND configuration is much smaller. However the series parasitic resistances and transistor conductance variations of this configuration cause voltage drops along the source or drain nodes which lower the dynamic range of the memory cell. More severe in the NAND structure, if considered for analog storage, is the fact that this voltage drop causes the output voltage of one particular cell in a string to be different in the read-back mode of the read/compare/write programming sequence than in the actual read mode for output or playback purposes, since the threshold voltages of other memory cells in the same string are frequently to be further modified depending on the signal inputs. Thus, a first cell in a string can appear to be properly programmed, but one or more other cells in the string require further programming by further programming pulses, so that these cells will have a different resistance when the contents of the first cell are to be later read out during playback from the resistance that existed when the first cell was determined to be properly programmed.